1. Field of the Invention
The present invention relates to a manufacturing method of a liquid crystal display. In particular, the invention relates to a manufacturing method of an active matrix liquid crystal display having thin-film transistors (hereinafter referred to as TFTs) as switching elements.
2. Description of the Related Art
Active matrix liquid crystal displays that are used as displays of OA equipment including computers are now attracting much attention as high-image-quality flat panel displays. Such active matrix liquid crystal displays are generally classified into the vertical electric field type and the horizontal electric field type. In vertical electric field type liquid crystal display panels, a liquid crystal is sealed between an array substrate in which TFTs and pixel electrodes are formed and an opposite substrate in which a common electrode is formed. When a voltage is applied between electrodes on both sides of the liquid crystal layer, an electric field develops approximately perpendicularly to the substrate surfaces. On the other hand, in horizontal electric field type liquid crystal display panels, not only TFTs and pixel electrodes but also a common electrode is formed in an array substrate. When a voltage is applied between electrodes, an electric field develops in a liquid crystal layer that is sealed between the array substrate and an opposite substrate in a direction approximately parallel with the substrate surfaces.
FIG. 14 is a substrate plan view of an array substrate of a vertical electric field type liquid crystal display panel as viewed from the liquid crystal layer side. As shown in FIG. 14, a plurality of data bus lines (drain bus lines) 101 are formed in the substrate so as to extend in the top-bottom direction in FIG. 14. A plurality of gate bus lines 103 (indicated by broken lines in FIG. 14) are also formed in the substrate so as to extend in the right-left direction in FIG. 14. A pixel is formed in each of regions that are defined by the data bus lines 101 and the gate bus lines 103. A TFT is formed in the vicinity of each of the intersecting points of the data bus lines 101 and the gate bus lines 103. A drain electrode 117 of the TFT shown in FIG. 14 branches off the left-hand data bus line 101 in FIG. 14 and has an end portion that is located over one side portion of a channel protective film 105 that is formed over the gate bus line 103 shown in FIG. 14.
On the other hand, a source electrode 119 is formed so as to overlap with the other side portion of the channel protective film 105. With the above structure, the portion of the gate bus line 103 right under the channel protective film 105 functions as a gate electrode of the TFT. Although not shown in FIG. 14, a gate insulating film is formed on the gate bus line 103 and a semiconductor active layer (semiconductor layer of operation) where a channel is to be formed is formed on the gate insulating film. As described above, in the TFT structure of FIG. 14, the gate electrode does not branch off the gate bus line 103 and, instead, part of the straight gate bus line 103 is used as the gate electrode. An auxiliary capacitor bus line 115 (indicated by broken lines in FIG. 14) is formed so as to extend in the right-left direction and to be located approximately at the center of the pixel region in the topbottom direction. A storage capacitor electrode 109 is formed over the auxiliary capacitor bus line 115 so as to coextend with it in the pixel region with an insulating film interposed in between (the storage capacitor electrodes 109 are formed for the respective pixels). A transparent pixel electrode 113 is formed above the source electrode 119 and the storage capacitor electrode 109. The pixel electrode 113 is electrically connected to the source electrode 119 via a contact hole 107 in a protective film that is formed under the pixel electrode 113. The pixel electrode 113 is also electrically connected to the storage capacitor electrode 109 via a contact hole 111.
Next, a manufacturing method of the liquid crystal display shown in FIG. 14 will be described with reference to FIGS. 15A and 15B to FIGS. 20A and 20B. In FIGS. 15A and 15B to FIGS. 20A and 20B, the same components as shown in FIG. 14 are given the same reference numerals as in FIG. 14. FIGS. 15A, 16A, 17A, 18A, 19A and 20A are sectional views of the TFT taken along line M-Mxe2x80x2 in FIG. 14, and FIGS. 15B, 16B, 17B, 18B, 19B, and 20B are sectional views of the storage capacitor portion taken along line N-Nxe2x80x2 in FIG. 14.
First, as shown in FIGS. 15A and 15B, a metal layer of about 150 nm in thickness is formed on a transparent glass substrate 121 by forming an Al (aluminum) film, for example, over the entire surface. Then, patterning is performed by using a first mask, whereby a gate bus line 103 (see FIG. 15A) and an auxiliary capacitor bus line 115 (see FIG. 15B) are formed. Then, a silicon nitride (SiN) film, for example, is formed over the entire substrate surface by plasma CVD, whereby a gate insulating film 123 is formed. Then, an amorphous silicon (a-Si) layer 125, for example, to be used for forming a semiconductor active film is formed over the entire substrate surface by plasma CVD. Further, a SiN film 127, for example, to be used for forming a channel protective film is formed over the entire surface by plasma CVD.
Then, back exposure is performed on the transparent glass substrate 121 with the gate bus line 103 and the auxiliary capacitor bus line 115 as a mask. Further, by using a second mask, a resist pattern (not shown) is formed over the gate bus line 103 in a self-aligned manner, and the portions of the silicon nitride film 127 over the gate bus line 103 and the auxiliary capacitor bus line 115 are etched away, whereby a channel protective film 105 is formed over the gate bus line 103 in the TFT forming region (see FIGS. 16A and 16B).
Then, as shown in FIGS. 17A and 17B, an n+a-Si layer 129 to be used for forming an ohmic contact layer is formed over the entire surface by plasma CVD. Then, a metal (e.g., Cr) layer 131 to be used for forming a drain electrode 117, a source electrode 119, a storage capacitor electrode 109, and a data bus line 101 is formed by sputtering.
Thereafter, as shown in FIGS. 18A and 18B, the metal layer 131, the n+a-Si layer 129, and the amorphous silicon layer 125 are patterned by using a third mask, whereby a data bus line 101 (not shown in FIGS. 18A and 18B), a drain electrode 117, a source electrode 119, a storage capacitor electrode 109, and a semiconductor active layer 106 are formed. In the etching of this patterning, the channel protective film 105 serves as an etching stopper, and hence the amorphous silicon layer 125 under the channel protective film 105 is left without being etched.
Thereafter, as shown in FIGS. 19A and 19B, a protective film 133 (e.g., a silicon nitride film) is formed by plasma CVD. Then, the protective film 133 is patterned by using a fourth mask, whereby contact holes 107 and 111 are formed through the protective film 133 over the source electrode 119 and the storage capacitor electrode 109, respectively.
Subsequently, as shown in FIGS. 20A and 20B, a pixel electrode forming layer 135 made of ITO, for example, is formed over the entire surface of the transparent glass substrate 121. Then, the pixel electrode forming layer 135 is patterned by using a fifth mask, whereby a pixel electrode 113 having a prescribed shape as shown in FIG. 14 is formed. The pixel electrode 113 is electrically connected to the source electrode 119 and the storage capacitor electrode 109 via the contact holes 107 and 111, respectively. A vertical electric field type liquid crystal display as shown in FIG. 14 is completed by executing the above process.
Next, the structure of a horizontal electric field type liquid crystal display will be described with reference to FIGS. 21 and 22. FIG. 21 is a substrate plan view of an array substrate of a horizontal electric field type liquid crystal display panel as viewed from the liquid crystal layer side. Referring to FIG. 21, a plurality of data bus lines 101 (only one data bus line 101 is shown in FIG. 21) are formed in the substrate so as to extend in the top-bottom direction in FIG. 21. A plurality of gate bus lines 103 (only one gate bus line 103 is shown in FIG. 21) are also formed in the substrate so as to extend in the right-left direction in FIG. 21, that is, so as to be perpendicular to the data bus lines 101. Each of regions that are defined by the data bus lines 101 and the gate bus lines 103 is a pixel region. A TFT is formed in the vicinity of each of the intersecting points of the data bus lines 101 and the gate bus lines 103. A drain electrode 117 of the TFT shown in FIG. 21 branches off the data bus line 101 shown in FIG. 21 and has an end portion that is located over one side portion of a channel protective film 105 that is formed over the gate bus line 103 shown in FIG. 21. One end portion of a pixel electrode 141 that also serves as a source electrode overlaps with the other side portion of the channel protective film 105 and is opposed to the drain electrode 117. With the above structure, the portion of the gate bus line 103 right under the channel protective film 105 functions as a gate electrode of the TFT. Although not shown in FIG. 21, a gate insulating film is formed on the gate bus line 103 and a semiconductor active layer where a channel is to be formed is formed between the gate insulating film and the overlying channel protective film 105.
In the TFT structure of FIG. 21, the gate electrode does not branch off the gate bus line 103 and, instead, part of the straight gate bus line 103 is used as the gate electrode. The pixel electrode 141 that also serves as the source electrode has a comb structure whose teeth extend downward in FIG. 21 from the base. In the pixel region of the substrate, an opposite electrode 143 is formed that has a comb structure whose teeth extend upward in FIG. 21 from the base and interdigitate with the teeth of the pixel electrode 141.
FIG. 22 is a schematic sectional view of the horizontal electric field type liquid crystal display panel taken along line P-Pxe2x80x2 in FIG. 21. A liquid crystal layer 155 is sealed between a transparent glass substrate 147 that constitutes an array substrate and a transparent glass substrate 163 that is opposed to the substrate 147 with a prescribed cell gap. In the array substrate, a polarizer 145, the transparent glass substrate 147, an undercoat insulating film 149, the pixel electrodes 141 and the opposed electrodes 143, the protective film 151, and an alignment film 153 are formed in this order from the light incidence side. On the other hand, in the opposite substrate, a polarizer 165, the transparent glass substrate 163, color filters 161, and an alignment film 159 are formed in this order from the light exit side.
The manufacturing method of this horizontal electric field type liquid crystal display panel is almost the same as that of the vertical electric field type liquid crystal display panel. However, there is a difference that in the horizontal electric field type the data bus lines 101, the drain electrodes 117, the pixel electrodes 141 that also serve as the source electrodes, and the opposite electrodes 143 can be formed by patterning using a single mask. Therefore, in contrast to the fact that five masks are necessary to manufacture the array substrate of the vertical electric field type liquid crystal display panel as described above with reference to FIGS. 15A and 15B to FIGS. 20A and 20B, the array substrate of the horizontal electric field type liquid crystal display panel can be manufactured by using four masks.
Incidentally, with the spread of active matrix liquid crystal displays, reduction of the manufacturing cost is an important subject that should be attained to supply liquid crystal displays at a low price in a stable manner. To reduce the manufacturing cost, first, increase of the production yield of liquid crystal display products is required strongly. Second, it is also necessary to increase the throughput of the manufacture of liquid crystal display products. To these ends, not only should the manufacturing process be simplified but also film forming processes and photolithography processes that are more sophisticated than the conventional ones need to be provided. However, there is a problem that introduction of higher-performance manufacturing equipment may increase the manufacturing cost. Further, in view of the recent increase in the resolutions of liquid crystal displays and the recent demand for large-size screens, the current manufacturing methods cannot increase the production yield and the throughput to a great extent. Still further, in the manufacture of a liquid crystal display, the manufacture of masks to be used in photolithography processes are costlier than in the manufacture of a semiconductor device. This is a factor of increasing the manufacturing cost. However, there is a problem that manufacturers are obliged to overlook this point with priority given to increase of the resolution of a liquid crystal display and increase of its screen size.
An object of the present invention is to provide a manufacturing method of a liquid crystal display that can reduce the manufacturing cost.
The above object is attained by a manufacturing method of a liquid crystal display, comprising the steps of:
forming a gate insulating film, a semiconductor film, and a first insulating film in this order on a substrate and gate bus lines that are formed on the substrate; forming channel protective films extending along the respective gate bus lines by performing back exposure using the gate bus lines as a mask and then patterning the first insulating film; forming, for each pixel region, on the associated channel protective film, a source electrode and a drain electrode that are opposed to each other; and forming, by etching away at least the associated channel protective film and the semiconductor film, two device isolation holes over the associated gate bus line at two locations that are on both sides of the source electrode and the drain electrode.